The present invention relates to the field of graphics processing, and in particular to a display list processor in a graphics subsystem for offloading graphics operations from a host processor.
Demand for sophisticated computer graphics has notably increased among consumers as graphics-based user interfaces displaying realistic icons, windows and the like have found widespread popularity. Advances in graphics software, including standardized graphics interfaces such as GKS (Graphics Kernel System) and PHIGS (Programmer""s Hierarchical Graphics Standard) have made applications which generate complex 2D and 3D images, including animated images, comparatively easy to code, and consequently more prevalent.
Typically, to perform graphics rendering, instructions in a high-level graphics application program must be reduced to hardware-level instructions suitable for issuing to physical display hardware, and then the display hardware must be managed and serviced during the execution of the hardware-level instructions. Display hardware is generally raster-based, which means that each display is created from pixel information generated from the instructions and stored in a memory location known as a frame buffer, corresponding to the display screen. In a CRT display, for example, the digital pixel information is converted by a video controller into analog signals which determine the intensity and color of an electron beam scanning corresponding points on the display screen at a suitable rate.
Thus, operations associated with graphical displays include filling or modifying a frame buffer with pixel information, refreshing the pixel information at a rate high enough to avoid a ragged or jerky appearance in display images, and handling interrupts generated by display hardware.
Tasks required to render even a simple image can place heavy demands on a processor. In early graphics systems, a single processor handled all of the graphics tasks. However, such a system can be quickly overwhelmed by the graphics demands of more sophisticated images, slowing rendering and frustrating users.
Accordingly, graphics accelerators have been developed which, in combination with other display hardware, can effect a graphics subsystem which acts to relieve a host processor from certain graphics operations. Such accelerators incorporate fundamental rendering functions at a hardware level, such as line drawing, circle and polygon drawing and filling, and bit-block-transfer. Accelerators can execute high-speed register instructions for performing these basic functions to write graphical elements to a frame buffer, thereby offloading from the host processor the requirements of actually performing the hardware-level instructions to fill or modify the frame buffer. However, in such an architecture, typically the host processor must still feed the graphics instructions to the registers of the accelerator, and handle such chores as display screen refreshes and other tasks generated by hardware interrupts from the graphics subsystem.
Thus, a further refinement which has been developed for graphics subsystems having an accelerator is the provision of a dedicated subsystem memory for holding what is known as a xe2x80x9cdisplay list.xe2x80x9d A display list is a set of instructions for performing graphics operations, assembled by a host processor and stored in the graphics subsystem memory for execution by the accelerator without host processor intervention. In place of the host processor, a unit known as a display list processor (DLP) issues instructions in a display list to the accelerator, introducing a degree of independence into operations by the graphics subsystem, and reducing the burden on the host processor.
Approaches to the design of graphics subsystems utilizing display lists and DLP""s vary widely in the art. Some approaches still require substantial host operations for communicating with and managing the DLP, and for handling hardware chores on the graphics subsystem.
In view of the foregoing, it is desirable to increase the independence of a graphics subsystem having a DLP, by reducing DLP management tasks for the host processor, and otherwise transferring functions usually performed by the host processor to the graphics subsystem, freeing the host processor for other necessary tasks.
A processing system according to the present invention utilizes a DLP which is capable of managing a graphics subsystem with a substantial degree of independence from a host processor. Once the DLP is initialized by the host processor, control of the DLP, and consequently, of the graphics subsystem, can be done entirely from the display list currently being processed.
In the general operation of the system, a host processor executes graphics application programs which generate graphics directives. The host processor organizes the directives into display lists and stores them in a memory accessible to the DLP.
The display lists generally comprise control directives and hardware function directives. Under the control of the control directives, the DLP issues the hardware function directives to graphics accelerators, which execute graphics operations in response thereto, to generate pixel information for display on a display device.
In an embodiment of the invention, the DLP includes registers which support the linking of a continuous series of operations with only nominal host processor operations being required. To assign work to the DLP, the host processor increments an incremental register in the DLP which indicates that one or more new display lists have been generated by the host processor and stored in the memory for processing by the DLP. Whenever this incremental register is updated, the DLP adds its contents to a second register in the DLP which maintains a count of display lists to be processed; the DLP then zeroes the incremental register. As long as the count in the second register is greater than zero, the DLP continues to process display lists. By communicating with the DLP through these registers, the host processor can link a continuous series of display lists together for processing by the DLP, and never needs to interrupt the DLP or determine its status in order to assign it new work.
The host processor may be further decoupled from graphics operations, according to the foregoing embodiment, by utilizing the DLP to perform functions triggered by hardware status signals which the DLP may be programmed to monitor through control directives in a display list. Registers in graphics accelerators which are readable by the DLP contain status information generated by hardware signals relating to graphics operations performed by the accelerators. The DLP also includes a register for status information on other selected hardware devices. These registers may be polled by the DLP under control of the control directives. The DLP monitors the registers, and delays or initiates specified operations depending on the status indicated in the registers. This feature allows the host processor to be decoupled from hardware interrupt handling for the graphics subsystem.
The foregoing features obtain optimum efficiency from a host processor and the graphics subsystem, allowing each to work at its maximum rate, and freeing the host processor to perform essential work unrelated to graphics processing.